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agilent HDMP-2630B/2631b 2.125/1.0625 gbd serdes circuits data sheet description this data sheet describes the HDMP-2630B/2631b serdes devices for 2.125 gbd serial data rates. references to sstl_2 in the text will also apply to sstl_3; however, there are separate tables and figures showing voltage values and connec- tion diagrams for these two logic families. the HDMP-2630B/2631b serdes are silicon bipolar integrated cir- cuits in a metallized qfp package. they provide a low-cost physical layer solution for 2.125 gbd serial link interfaces including a complete serialize/deserialize (serdes) func- tion with transmit and receive sec- tions in a single device. the HDMP-2630B/2631b are also ca- pable of operating on 1.0625 gbd serial links. input pins tx_rate and rx_rate select the data rates on the transmit and receive sides respectively. as shown in figure 1, the transmit- ter section accepts 10-bit wide parallel sstl_2 data (tx[0:9]) and a 106.25 mhz sstl_2 byte clock (tbc) and serializes them into a features ? 10-bit wide parallel tx, rx busses ? 106.25 mhz tbc and rbc[0:1] ? option to set tx and rx serial data rates separately ? parallel data i/o, clocks and control compatible with sstl_2 (HDMP-2630B) or sstl_3 (hdmp-2631b) ? differential pecl or lvttl refclk at 106.25 mhz or 53.125 mhz ? double data rate transfers ? source synchronous clocking of transmit data ? source centered or source synchronous clocking of receive data ? dual or single receive byte clocks ? parallel loopback mode ? differential bll serial i/o with on-chip source termination ? 14 mm, 64-pin mqfp package ? single +3.3v power supply applications ? fibre channel arbitrated loop and trunks ? fast serial backplanes ? clusters ordering information part number parallel i/o HDMP-2630B sstl_2 hdmp-2631b sstl_3 high-speed serial stream. the parallel data is expected to be 8b/10b encoded data or equiva- lent. at the source, tx[0:9] and tbc switch synchronously with respect to a 106.25 mhz clock internal to the sender. new data are emitted on both edges of tbc; this is called double data rate (ddr). the HDMP-2630B/ 2631b find a sampling window between the two edges of tbc to latch tx[0:9] data into the input register of the transmitter section when tx_rate =1. if tx_rate = 0, the user must ensure no data transitions on the falling edge of tbc and this edge is used to latch in parallel data resulting in a 1.0625 gbd serial stream. the transmitter sections pll locks to the 106.25 mhz tbc. this clock is then multiplied by 20 to generate the 2125 mhz serial clock for the high-speed serial outputs. the high speed outputs are capable of interfacing directly to copper cables or pcb traces for electrical transmission or to a separate fiber optic module for optical transmission.
2 the high-speed outputs include user-controllable skin-loss equal- ization to improve performance when driving copper lines. the receiver section accepts a serial electrical data stream at 1.0625 or 2.125 gbd and recovers 10-bit wide parallel data. the receiver pll locks onto the incoming serial signal and recov- ers the high-speed incoming clock and data. the serial data is converted back into 10-bit parallel data, optionally recogniz- ing the first seven bits of the k28.5+ comma character to establish byte alignment. if k28.5+ detection is enabled, the receiver section is able to detect comma characters at 1.0625 gbd or 2.125 gbd depending on the value of the rx_rate pin. the recovered parallel data is presented at sstl_2 compatible outputs rx[0:9], along with a pair of 106.25 mhz sstl_2 clocks, rbc[0] and rbc[1], that are 180 degrees out of phase from one another and which rep- resent the remote clock. rising edges of rbc[0] and rbc[1] may be used to latch rx[0:9] data at the destination. for short distances, there may be a need to have asics communi- cate directly using parallel tx and rx lines without the serdes inter- mediary. to enable this, the tx and rx parallel timing schemes must be symmetrical. when rbc_sync = 1 and rx_rate = 1 such symmetry is obtained. in this mode, the rx[0:9] lines switch simulta- neously with the rising and falling edges of rbc[1] or rbc[0] just as the tx[0:9] lines switch simultaneously with tbc. if rx_rate = 0 and rbc_sync = 1 then the rx[0:9] lines switch with the rising edges of rbc[1] just as the tx[0:9] lines switch with the rising edges of tbc. if rbc_sync = 0 then rx[0:9] data may be latched on the rising edges of rbc[1] and rbc[0]. in this latter mode, the rbc[0:1] clocks operate at a 53.125 mhz rate. in summary, by setting rbc_sync = 0 the timing of transmit and receive parallel data with respect to tbc and rbc[0:1] may be arranged so that the upstream protocol device can generate and latch data very simply. this is the source cen- tered mode of operation (case a and c in table 1, page 8). alter- natively, setting rbc_sync = 1 provides for timing symmetry between tx and rx parallel lines at both 1.0625 gbd and 2.125 gbd rates. this is the source synchronous mode of operation (case b and d in table 1, page 8). note when en_cdet = 1, the first transition of byte 0 of a comma will either coincide with the rising edge of rbc[1] or precede it. this applies regard- less of the rx_rate setting. table 1 summarizes the behavior of the rx parallel section under all values of rx_rate and rbc_sync. for test purposes, the transceiver provides for on- chip parallel to parallel local loopback functionality controlled through the ewrap pin. addi- tionally, the byte alignment fea- ture via detection of the first seven bits of the k28.5+ charac- ter may be disabled. this may be useful in proprietary applications which use alternative methods to align the parallel data. the HDMP-2630B/2631b accept either a differential pecl or a lvttl reference clock input. this input may be full rate (106.25 mhz, ref_rate = 0) or half rate (53.125 mhz, ref_rate = 1). HDMP-2630B/2631b block diagram the HDMP-2630B/2631b (figure 2) are designed to transmit and receive 10-bit wide parallel data over high-speed serial communi- cation lines. the parallel data applied to the transmitter is expected to be encoded per the 8b/10b encoding scheme with special reserved characters for link management purposes. other encoding schemes will also work as long as they provide dc bal- ance and a sufficient number of transitions. the HDMP-2630B/ 2631b incorporate the following: ? sstl_2 or sstl_3 parallel i/o ? high speed phase locked loops ? parallel to serial converter ? high speed serial clock and data recovery circuitry ? comma character recognition per fibre channel specifications ? byte alignment circuitry ? serial to parallel converter input latch the transmitter accepts 10-bit wide single ended sstl_2 parallel data at inputs tx[0:9]. the sstl_2 tbc clock provided by the sender of the transmit data is used as the transmit byte clock. the tx[0:9] and tbc signals must be properly aligned as shown in figure 3. if tx_rate = 1, tx[0:9] data are latched between both edges of tbc. if tx_rate = 0, tx[0:9] data are latched on the falling edge of tbc. the tx[0:9] and tbc inputs are unterminated sstl_2 inputs per section 4.1 of the sstl_2 standard and section 3.3.1 of the sstl_3 standard (figure 11).
3 figure 1. typical application using HDMP-2630B/2631b. figure 2. block diagram of HDMP-2630B/2631b. so tx pll clock generator refclk[0:1] tx_rate rx_rate rbc[0:1] com_det en_cdet output driver tx clocks input latch rx[0:9] txcap1 txcap0 tx[0:9] rx clocks ewrap output select frame mux rx pll clock recovery input select frame demux and byte sync input sampler ref_rate rbc_sync si tbc rxcap0 rxcap1 HDMP-2630B/2631b asic so receiver section pll transmitter section com_det refclk[0:1] si pll rbc[0:1] en_cdet rx_rate ref_rate rbc_sync rx[0:9] ewrap tx[0:9] tbc tx_rate
4 tx pll/clock generator the transmitter phase locked loop and clock generator block is responsible for generating all internal clocks needed by the transmitter section to perform its functions. these clocks are based on the supplied transmit byte clock (tbc). incoming data must be synchronous with tbc (figures 3a-3b). use of tbc to determine sampling points to latch data obviates the need for plls in the data source. frame mux the frame mux accepts 10-bit wide parallel data from the input latch. using internally generated high-speed clocks, this parallel data is multiplexed into a 2.125 gbd serial data stream. the data bits are transmitted sequentially from tx[0] to tx[9]. the leftmost bit of k28.5+ is on tx[0]. output select the output select block picks the serial data to drive on to the serial output line. in normal operation, the serialized tx[0:9] data is placed at so . in parallel loopback (ewrap=1) mode, the so pins are held static at logic 1 and the internal serial output signal going to the input select block of the receiver section is used to gener- ate rx[0:9]. in addition, the output select block allows the user to control the amount of pre-emphasis used on the so pins. if pre-emphasis is used, 0 ? 1 and 1 ? 0 transitions on so have greater amplitude than 0 ? 0 and 1 ? 1 transitions. this increased amplitude is used to offset the effects of skin loss and dispersion on long pcb transmis- sion lines. pre-emphasis is con- trolled by the eqamp pin (table 2 and figure 9). input select the input select block picks the serial data that will be parallelized to drive rx[0:9]. in normal operation, serial data is accepted at si . in parallel loopback (ewrap = 1) mode, the internal serial output signal from the output select block of the transmitter section is used to generate rx[0:9]. rx pll/clock recovery the receiver phase locked loop and clock recovery block is responsible for frequency and phase locking onto the incoming serial data stream and recovering the bit and byte clocks. an auto- matic locking feature allows the rx pll to lock onto the input data stream without external pll training controls. it does this by continually frequency locking onto the 106.25 mhz reference clock, and then phase locking onto the selected input data stream. an internal signal detec- tion circuit monitors the presence of the input and invokes the phase detection as the data stream appears. once bit locked, the receiver generates the high speed sampling clock for the input sampler. input sampler the input sampler is respon- sible for converting the serial input signal into a retimed bit stream. to accomplish this, it uses the high-speed serial clock generated from the rx pll/ clock recovery block. this serial bit stream is sent to the frame demux and byte sync block. frame demux and byte sync the frame demux and byte sync block is responsible for restoring the 10-bit parallel data from the high-speed serial bit stream. this block is also responsible for recognizing the first seven bits of the k28.5+ positive disparity comma charac- ter (0011111xxx). when recog- nized, the frame demux and byte sync block works with the rx pll/clock recovery block to select the proper parallel data edge out of the bit stream so that the next comma character starts at rx[0]. when a comma character is detected and realign- ment of the receive byte clock rbc[0:1] is necessary, these clocks are stretched (never sliv- ered) to the next correct align- ment position. rbc[0:1] will be aligned by the start of the next ordered set (four-byte group) after k28.5+ is detected. the start of the next ordered set will be aligned with the rising edge of rbc[1], independent of the rx_rate pin setting. per the fibre channel encoding scheme, comma characters must not be transmitted in consecutive bytes so that the receive byte clocks may maintain their proper recov- ered frequencies. output drivers the output drivers present the 10-bit parallel recovered data (rx[0:9]) properly aligned to the receive byte clock (rbc[0:1]) as shown in figures 5a-5d and table 1. these output drivers provide single ended sstl_2 compatible signals.
5 receiver loss of signal the receiver loss of signal block examines the peak-to-peak differential amplitude at the si input. when this amplitude is too small, rx_los is set to 1, and rx[0:9] are set to logic one (1111111111). this prevents generation of random data at the rx[0:9] pins when the serial input lines are disconnected. when the signal at si is a valid amplitude, rx_los is set to logic 0, and the output of the input select block is passed through. sstl_2 compatibility the HDMP-2630B works with protocol (fc-1 or mac) devices whose vddq voltage is nominally 2.5 v. note that the hdmp- 2630b works with a single v cc supply of 3.3 v. nonetheless, rx[0:9] and rbc[0:1] generate output voltages that are compat- ible with section 4.1 of the sstl_2 standard and are not meant to be terminated in 50 w . in addition, the HDMP-2630B provides a vrefr output pin which may be used at the proto- col ic in order to differentially detect a high or a low on rx[0:9]. alternatively, this volt- age may be generated on the pcb using a resistor divider from vddq or v cc while ignoring the vrefr output of the hdmp- 2630b. the HDMP-2630B ex- pects sstl_2 compatible signals at the tx[0:9] and tbc pins. these pins are unterminated per section 4.1 of the sstl_2 stan- dard (figure 11). the vreft input pin is used by the hdmp- 2630b to differentially detect a high or low on tbc and tx[0:9]. vreft may be generated by the protocol device or on the pcb using a resistor divider from v ddq or v cc . sstl_3 compatibility the hdmp-2631b works with protocol (fc-1 or mac) devices whose vddq voltage is nominally 3.3v. rx[0:9] and rbc[0:1] generate output voltages that are compatible with section 3.3.1 of the sstl_3 standard and are not meant to be terminated in 50 w . in addition, the hdmp-2631b provides a vrefr output pin which may be used at the proto- col ic in order to differentially detect a high or a low on rx[0:9]. alternatively, this volt- age may be generated on the pcb using a resistor divider from vddq or v cc while ignoring the vrefr output of the hdmp- 2631b. the hdmp-2631b ex- pects sstl_3 compatible signals at the tx[0:9] and tbc pins. these pins are unterminated per section 3.3.1 of the sstl_3 stan- dard (figure 11). the vreft input pin is used by the hdmp- 2631b to differentially detect a high or low on tbc and tx[0:9]. vreft may be generated by the protocol device or on the pcb using a resistor divider from vddq or v cc . multi-rate operation the HDMP-2630B/2631b provide hooks for initializing multi-rate links. a possible algorithm oper- ates as follows. in a point to point link, each node sets its tx_rate input pin high to transmit at the highest possible data rate. at the same time, each node tries differ- ent values of rx_rate to see at which data rate intelligible data is received. once this data rate is found, tx_rate is set to enable this rate. for example, suppose a node that is capable of operating at 1.0625 gbd and 2.125 gbd rates is establishing a link with a node that is capable of only 2.125 gbd. both nodes will start emitting at 2.125 gbd because this is their highest rate. the first node will try receiving at 1.0625 gbd rate. it will not suc- ceed and will therefore try 2.125 gbd reception, which will succeed. the second node is set to 2.125 gbd and has been receiving correct data. these two nodes will settle to 2.125 gbd. if the second node in the example above operated at 1.0625 gbd only, then the first node would see intelligible 1.0625 gbd data and set its tx_rate = 0, at which time the second node would also start seeing intelligible data. these nodes would settle to 1.0625 gbd. if both nodes are 1.0625/2.125 gbd capable, then they will settle to 2.125 gbd. with this algorithm, nodes need not have a common lowest common denominator data rate to interoperate.
6 HDMP-2630B/2631b transmitter section timing characteristics t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. t txct tx[0:9] input data and tbc clock transition range (tx_rate = 1) ps 1880 t txcv tx[0:9] input data and tbc clock valid time (tx_rate = 1) ps 2820 t txsetup tx[0:9] setup time to falling edge of tbc (tx_rate = 0) ps 1400 t txhold tx[0:9] hold time from falling edge of tbc (tx_rate = 0) ps 1400 t_txlat [1] transmitter latency ns 0.8+ bits 8.5 note: 1. the transmitter latency, as shown in figure 4, is defined as the time between the leading edge of a parallel data word and the leading edge of the first transmitted serial output bit of that data word. figure 3a. parallel transmitter section timing. tx_rate = 1. figure 3b. parallel transmitter section timing. tx_rate = 0. tx[0:9] 9.41 ns txcv txcv txct tbc tx[0:9] 9.41 ns txsetup txhold tbc
7 figure 4. transmitter latency. tx[0] is first bit on so . 10-bit char b tx[0..9] 10-bit char a so 10-bit char b txlat 10-bit char c tbc tx[0] HDMP-2630B/2631b receiver section timing characteristics t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. f_lock frequency lock at powerup with refclk active m s 500 b_sync [1,2] bit sync time bits 200 2500 t_rxlat [3] receiver latency ns 13.5 bits +2.5 notes: 1. this is the recovery time for input phase jumps, per the fibre channel specification x3.230-1994 fc-ph standard, sec 5.3. 2. tested using c pll = 0.1 m f. 3. the receiver latency, as shown in figure 6, is defined as the time between the leading edge of the first received serial bit of a parallel data word and the leading edge of the corresponding parallel output word.
8 table 1. HDMP-2630B/2631b rx, rbc[0:1] timing dependence on rx_rate and rbc_sync. input settings resulting behaviors case rx_rate rbc_sync si rate (gbd) rbc rate (mhz) timing diagrams for rbc0, rbc1, rx[0:9] a 0 0 1.0625 53.125 b 0 1 1.0625 106.25 c 1 0 2.125 106.25 d 1 1 2.125 106.25 rbc0 rbc1 rx[0:9] rbc0 rbc1 rx[0:9] rbc0 rbc1 rx[0:9] rbc0 rbc1 rx[0:9] figure 5. test conditions for sstl_2 and sstl_3 output drivers. measurement point z0 = 50 w cload = 4-20 pf ?00 ? <= iload <= 100 ? sstl output driver delay = 0.5 - 2.0 ns
9 figure 5a. receiver section timing C case a. case a of table 1. (rx_rate = 0, rbc_sync = 0) t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. t rxs rx[0:9] setup time to rbc1 or rbc0 (data valid before) ps 2700 t rxh rx[0:9] hold time from rbc1 or rbc0 (data valid after) ps 1500 t a-b rbc1 rising edge to rbc0 rising edge skew ns 8.9 9.9 t duty rbc[0:1] duty cycle % 40 60 rx[0:9] rxs 18.82 ns rbc1 rbc0 rxh rxs rxh t a-b
10 figure 5b. receiver section timing C case b. case b of table 1. (rx_rate = 0, rbc_sync = 1) t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. t rxs rx[0:9] setup time to rbc1 or rbc0 (data valid before) ps 1700 t rxh rx[0:9] hold time from rbc1 or rbc0 (data valid after) ps 1700 rx[0:9] 9.41 ns rbc0 rxs rxh rbc1 figure 5c. receiver section timing C case c. case c of table 1. (rx_rate = 1, rbc_sync = 0) t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. t rxs rx[0:9] setup time to rbc1 or rbc0 (data valid before), HDMP-2630B ps 1400 rx[0:9] setup time to rbc1 or rbc0 (data valid before), hdmp-2631b 1200 t rxh rx[0:9] hold time from rbc1 or rbc0 (data valid after), HDMP-2630B ps 1400 rx[0:9] hold time from rbc1 or rbc0 (data valid after), hdmp-2631b 1200 t a-b rbc1 rising edge to rbc0 rising edge skew ns 4.5 4.9 t duty rbc[0:1] duty cycle % 40 60 rx[0:9] rxs 9.41 ns rbc1 rbc0 rxh rxs rxh t a-b
11 figure 5d. receiver section timing C case d. case d of table 1. (rx_rate = 1, rbc_sync = 1) t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. t rxct rx[0:9] output data and rbc clock transition range ps 1700 t rxcv rx[0:9] output data and rbc clock valid time ps 3000 figure 6. receiver latency. first bit on si drives rx[0]. rx[0:9] 9.41 ns rbc1 rbc0 rxcv rxct 10-bit char b rx[0:9] 10-bit char b si 10-bit char c rxlat 10-bit char a rbc[0:1] rx[0] rx[9]
12 HDMP-2630B/2631b absolute maximum ratings sustained operation at or beyond any of these conditions may result in long-term reliability degradation or permanent damage, and is not recommended. symbol parameter units min. max. v cc supply voltage v C0.5 4.0 t stg storage temperature c C65 150 t c case temperature c0 95 t j junction temperature c 0 125 v in,pecl lvpecl input voltage v C0.5 v cc + 0.5 [1] v in,sstl sstl_2 or sstl_3 input voltage v C0.5 v cc + 0.5 [1] HDMP-2630B/2631b guaranteed operating rates t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v parallel clock rate (mhz) serial baud rate (gbd) serial baud rate (gbd) min. max. min. max. min. max. 106.20 106.30 1.062 1.063 2.124 2.126 HDMP-2630B/2631b transceiver refclk and tbc requirements t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. f nominal frequency mhz 106.25 f tol frequency tolerance ppm C100 100 symm symmetry (duty cycle) % 40 60 HDMP-2630B/2631b dc electrical specifications t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. i cc, trx [1] transceiver supply current (total of all supplies) ma 580 750 p d, trx [1] transceiver total power dissipation mw 1900 2600 note: 1. must remain less than or equal to absolute maximum v cc voltage of 4.0 v. note: 1. measurement conditions: tested sending 2.125 gbd 2 7 -1 prbs sequence from a serial bert with so outputs differentially terminated using a 150 w resistor. HDMP-2630B/2631b lvpecl dc electrical specifications for refclk[0:1] t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. v ih,pecl lvpecl input high voltage level v 2.10 2.60 v il,pecl lvpecl input low voltage level v 1.30 1.80 HDMP-2630B/2631b lvttl dc electrical specifications for refclk[1] t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. v ih,lvttl lvttl input high voltage level v 2.00 v il,lvttl lvttl input low voltage level v 0.80
13 sstl_2 i/o parameters HDMP-2630B recommended dc operating conditions and dc electrical characteristics t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v, vddq = 2.30 v to 2.70 v. vddq is the fc-1/mac device i/o supply voltage. sstl-2 inputs can receive lvttl signals successfully. sstl-2 outputs do not output lvttl compliant levels. symbol parameter units min. typ. max. vreft sstl_2 input reference voltage v 1.15 1.25 1.35 v ih input high voltage v vreft +0.35 vddq +0.30 v il input low voltage v C0.30 vreft C0.35 vrefr sstl_2 output reference voltage v 1.15 1.25 1.35 v oh output high voltage v vrefr +0.38 vddq v ol output low voltage v gnd vrefr C0.38 HDMP-2630B/2631b ac electrical specifications t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. t r,refclk refclk[0:1] pecl input rise time, v il,pecl to v ih,pecl ns 1.5 t f,refclk refclk[0:1] pecl input fall time, v ih,pecl to v il,pecl ns 1.5 t rd, hs_out hs_out differential rise time, 20% - 80% ps 160 t fd, hs_out hs_out differential fall time, 20% - 80% ps 160 t r,sstl sstl input rise time, v il,sstl to v ih,sstl ns 1.5 t f,sstl sstl input fall time, v ih,sstl to v il,sstl ns 1.5 v ip,hs_in hs_in input peak-to-peak differential voltage mv 200 2000 v op,hs_out [1] hs_out output pk-pk diff. voltage (z0 = 50 w , fig.9) mv 800 1050 2000 v op,hs_out [1] hs_out output pk-pk diff. voltage (z0 = 75 w , fig.9) mv 1100 1400 2000 note: 1. output differential voltage defined as (so+ C soC). measurement made with tx pre-emphasis off (eqamp tied to v cc with a 100 w resistor). sstl_3 i/o parameters hdmp-2631b recommended dc operating conditions and dc electrical characteristics t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v, vddq = 3.00 v to 3.60 v. vddq is the fc-1/mac device i/o supply voltage. sstl-3 inputs can receive lvttl signals successfully. sstl-3 outputs do not output lvttl compliant levels. symbol parameter units min. typ. max. vreft sstl_3 input reference voltage v 1.30 1.50 1.70 v ih input high voltage v vreft +0.40 vddq +0.30 v il input low voltage v C0.30 vreft C0.40 vrefr sstl_3 output reference voltage v 1.30 1.50 1.70 v oh output high voltage v vrefr +0.43 vddq v ol output low voltage v gnd vrefr C0.43
14 notes: 1. defined by fibre channel specification x3.230-1994 fc-ph, annex a, section a.4.4 (oscilloscope method) and tested using the setup shown in figure 8b. 2. defined by fibre channel specification x3.230-1994 fc-ph, annex a, section a.4.3 and tested using the setup shown in figure 8a. 3. defined in the fibre channel technical report methodologies for jitter specification, annex b, and tested using the setup shown in figure 8a. HDMP-2630B/2631b transmitter section output jitter characteristics t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units typ. rj [1] random jitter at so (1 s deviation of the 50% crossing point) ps 6.2 dj [2] deterministic jitter at so (peak-to-peak), k28.5+/k28.5C pattern ps 22 dj deterministic jitter at so (peak-to-peak), crpat [3] pattern ps 31 figure 7a. serial output eye diagram with nominal tx pre-emphasis. figure 7b. serial output random jitter with tx pre-emphasis off.
15 figure 8a-b. transmitter deterministic and random jitter measurement method. note: 1. based on independent package testing by agilent. q ja for these devices is 38 c/w for the HDMP-2630B and hdmp-2631b. q ja is measured on a standard 3x3" fr4 pcb in a still air environment. to determine the actual junction temperature in a given application, use the following equation: tj = tc + ( q jc x p d ), where tc is the case temperature measured on the top center of the package and p d is the power being dissipated. HDMP-2630B/2631b thermal characteristics t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units typ. q jc [1] thermal resistance, junction to case c/w 9.3 serial bert clock in data in hp 70004a display hp 70842a error detector hp 70841a pattern generator hp 70311a clock source clock out clock out modulation data out clock in clock out data out+ trigger n/c div 2 div 10 divide by 20 HDMP-2630B hdmp-2631b 2.125 gbd serdes hp 83480a scope deterministic jitter measurement method trigger from pgen clock or trigger rbc1 tbc si so refclk 106.25 mhz 10 bits 2.125 ghz serial bert clock in data in hp 70004a display hp 70842a error detector hp 70841a pattern generator hp 70311a clock source clock out clock out modulation data out clock in clock out data out+ trigger n/c div 2 div 10 divide by 20 HDMP-2630B hdmp-2631b 2.125 gbd serdes hp 83480a scope random jitter measurement method trigger from pgen clock or trigger tbc so refclk 106.25 mhz 2.125 ghz tx[0:9] static k28.7 0011111000
16 HDMP-2630B/2631b pin input capacitance symbol parameter units typ. c input input capacitance on sstl input pins pf 1.6 figure 9. tx pre-emphasis control using eqamp pin. v cc hs_out zo = 75 w zo = 75 w v cc_txhs gnd esd protection ?o +so gnd_txhs +si ?i esd protection + hs_in v cc gnd gnd v cc note: hs_in inputs should never be connected to ground as permanent damage to the device may result. z0 = 50 w may also be used. zo zo 0.01 ? 0.01 ? + figure 10. hs_out and hs_in simplified circuit schematic for HDMP-2630B/1b. steady-state output level 1 bit maximum output level (so+) ?(so? steady-state output level maximum output level eqamp setting 1.11 v 1.11 v 100 w to v cc (no pre-emphasis) 820 mv 1.28 v floating (nominal pre-emphasis) 570 mv 1.44 v shortened to gnd (maximum pre-emphasis) all values measured in a 50 w environment with v cc = 3.3 v and t a = 25?.
17 i/o type definitions i/o type definition i-sstl2 or i-sstl_3 input sstl_2 or sstl_3. these inputs will receive lvttl-compliant signals successfully. o-sstl2 or o-sstl_3 output sstl_2 or sstl_3. these outputs will not produce lvttl-compliant signals. hs_out high speed output, ecl compatible hs_in high speed input c external circuit node s power supply or ground figure 11. i-sstl2/i-sstl3 and o-sstl2/o_sstl3 simplified circuit schematic. vrefr v cc rx[0:9] tx[0:9] vreft HDMP-2630B hdmp-2631b r1 r2 v cc (mac) vreft v cc datain dataout mac v cc (serdes) = 3.3 v v cc (mac) = 2.5 v or 3.3 v vddq 2.5 v for sstl_2 3.3 v for sstl_3 rs = 50 w use termination, if necessary, to deliver proper voltage swings at tx[0:9] rs = 50 w unterminated 0.1 ? r1 r2 v cc (serdes) 0.1 ? note: vrefr on each device may be used to drive vreft on the other device instead of using the configuration above. vrefr should be bypassed with 0.1 ? in this case. if used, r1 + r2 should be 500-1000 w . 1% resistors should be used for r1 and r2. when using the configuration above, vreft to the mac device should be set to 1.25 v nominal (HDMP-2630B) and 1.5 v nominal (hdmp-2631b). using these values centers vrefr relative to the rx[0:9] output swings provided by the HDMP-2630B and hdmp-2631b. vrefr
18 table 2. pin definitions for HDMP-2630B/2631b name pin type signal eqamp 56 c output equalization amplitude control: controls the relative amount of equalization on the high-speed serial data outputs. equalization is disabled by connecting a 100 w resistor from eqamp to v cc . the amount of equalization can be increased by either increasing the value (above 100 w ) of a resistor connected from eqamp to v cc , or decreasing the value of a resistor connected from eqamp to gnd. maximum equalization is obtained by connecting eqamp directly to gnd. see figure 9. ewrap 19 i-sstl2 loop enable: when high, the high speed serial output data is internally connected directly to the receiver circuit, bypassing the high-speed input and output buffers. the external high-speed data outputs so are set high and si inputs are ignored. en_cdet 24 i-sstl2 comma detect enable: when high, enables detection of comma character. com_det 27 o-sstl2 comma detect indicator: when high, indicates that a comma character of positive disparity (0011111xxx) has been detected on the high speed serial input line. tx_rate 14 i-sstl2 transmit rate set: if set to low, the HDMP-2630B/2631b read tx[0:9] data on the falling edge of tbc and serializes it. this corresponds to a 1.0625 gbd serial stream. if set to high, the HDMP-2630B/2631b read tx[0:9] data between both edges of tbc and serializes it. this corresponds to a 2.125 gbd serial stream. rx_rate 55 i-sstl2 receive rate set: if set to low, the HDMP-2630B/2631b sample the incoming serial stream at 1.0625 gbd and drives it on the rx[0:9] lines with the rising edge of rbc1. if set to high, the HDMP-2630B/2631b sample the incoming serial stream at 2.125 gbd and drives it on the rx[0:9] lines with the rising edges of rbc1 and rbc0. (table 1.) ref_rate 29 i-sstl2 refclk rate: set this pin to low when using full rate (106.25 mhz) refclk[0:1] inputs. set this pin high when using half rate (53.125 mhz) refclk[0:1] inputs. ref_rate applies for both differential pecl or lvttl reference clock inputs. rbc_sync 10 i-sstl2 receive byte clock synchronization control: when rbc_sync=1, rx[0:9] data has the same relation to rbc[0:1] as tx[0:9] data has to tbc. asics designed using this mode have the option of avoiding a serdes driven serial link and communicating directly on parallel lines, for short distances. rx_los 26 o-sstl2 loss of signal at the receiver detect: indicates a loss of signal on the high-speed differential inputs, si , as in the case where the transmission cable becomes disconnected. if si >= 200mv peak-to-peak differential, rx_los = logic 0. if si < 200mv and si > 75mv, rx_los = undefined. if si =< 75mv, rx_los = logic 1, rx[0:9]=1111111111. so+ 62 hs_out serial data outputs: high speed outputs. these lines are active when not in parallel soC 61 loop mode (ewrap=0). when ewrap is high, these outputs are held static at logic 1. si+ 54 hs_in serial data inputs: high speed inputs. serial data is accepted from si inputs when siC 52 ewrap is low. tbc 01 i-sstl2 transmit clock: both edges of this input are used to determine the sampling window for transmit parallel data. refclk[1] 22 i-pecl reference clock: a 106.25 mhz (ref_rate = 0) or 53.125 mhz (ref_rate = 1) clock or supplied by the host system. it serves as the reference clock for the receive portion i-lvttl of the transceiver. these pins may be driven by a differential pecl clock source or a single ended lvttl clock source. in the lvttl case, refclk[1] is to be driven and refclk[0] 23 i-pecl refclk[0] is to be bypassed to gnd via a 0.1 m f capacitor. rbc[1] 30 o-sstl2 receive byte clocks: the receiver section recovers two receive byte clocks. these rbc[0] 31 two clocks are 180 degrees out of phase. see table 1 for timing relationships.
19 table 2. pin definitions for HDMP-2630B/2631b, continued name pin type signal tx[0] 02 i-sstl2 data inputs: one 10-bit, encoded character to the so serial outputs. tx[0] is the first tx[1] 03 bit transmitted. tx[0] is the least significant bit. tx[2] 04 tx[3] 06 tx[4] 07 tx[5] 08 tx[6] 09 tx[7] 11 tx[8] 12 tx[9] 13 rx[0] 45 o-sstl2 data outputs: one 10-bit encoded character from one of the si serial inputs. rx[0] is rx[2] 43 the first bit received. when rx_los =1, there is a loss of input signal at si , and these rx[3] 41 outputs are held static at logic 1. refer to rx_los pin definition for more details. rx[4] 40 rx[5] 39 rx[6] 38 rx[7] 36 rx[8] 35 rx[9] 34 txcap0 17 c loop filter capacitor: a loop filter capacitor for the internal transmit pll must be txcap1 16 connected across the txcap0 and txcap1 pins. (typical value is 0.1 m f) rxcap0 48 c loop filter capacitor: a loop filter capacitor for the internal receive pll must be rxcap1 49 connected across the rxcap0 and rxcap1 pins. (typical value is 0.1 m f) v cc 20 s logic power supply: normally 3.3 volts. used for internal pecl logic. 28 57 59 53 v cc _txa 18 s analog power supply : normally 3.3 volts. used to provide a clean supply line for transmit pll and high speed analog cells. v cc _rxa 50 s analog power supply: normally 3.3 volts. used to provide a clean supply line for receive pll and high speed analog cells. v cc _txhs 60 s high speed supply: normally 3.3 volts. used only for the high speed transmit cell 63 (hs_out). noise on this line should be minimized for best operation. vreft 05 s voltage reference input: used with i-sstl2 and i-sstl3 inputs to the HDMP-2630B/2631b. (figure 11.) vrefr 47 s voltage reference output: used with o-sstl2 and o-sstl3 outputs from the HDMP-2630B/2631b. (figure 11.) v cc _sstl 37 s sstl i/o supply voltage for sstl_2 and sstl_3 i/o. normally 3.3 v. all necessary 42 voltages for sstl_2 and sstl_3 operation are internally generated. gnd 21 s logic ground: normally 0 volts. this ground is used for internal pecl logic. 25 58
20 table 2. pin definitions for HDMP-2630B/2631b, continued name pin type signal gnd_txa 15 s analog ground: normally 0 volts. used to provide a clean ground plane for the pll and high-speed analog cells. gnd_rxa 51 s analog ground: normally 0 volts. used to provide a clean ground plane for the receiver pll and high-speed analog cells. gnd_txhs 64 s high speed ground: normally 0 volts. used for hs_in cell. gnd_sstl 32 s sstl ground: normally 0 volts. used for sstl_2 and sstl_3 i/o. 33 46 figure 12. recommended power supply filtering arrangement. rxcap0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 gnd_txhs ui HDMP-2630B/1b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vrefr gnd_sstl rx[0] rx[1] rx[2] v cc _sstl rx[3] rx[4] rx[5] rx[6] v cc _sstl rx[7] rx[8] rx[9] gnd_sstl tbc tx[0] tx[1] tx[2] vreft tx[3] tx[4] tx[5] tx[6] rbc_sync tx[7] tx[8] tx[9] tx_rate gnd_txa txcap1 v cc _txhs so+ so v cc _txhs v cc gnd v cc eqamp rx_rate si+ v cc si gnd_rxa v cc _rxa rxcap1 txcap0 v cc _txa ewrap v cc gnd refclk[1] refclk[0] en_cdet gnd com_det v cc ref_rate rbc[1] rbc[0] gnd_sstl rx_los 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 cpllt 0.1 ? v cc notes: 1. c1*-c4* for low-frequency bypass. 2. venkel part number c0603x7r160-104kne, or similar, can be used for 0.1 ? capacitors. 3. tdk p/n nl322522t-1r0j, or similar, can be used for 1 ? inductors. cb12 0.1 ? cb2 0.1 ? cb3 0.1 ? cb4 0.1 ? c1* 10 ? cb1 0.1 ? v cc + cpllr 0.1 ? cb5 0.1 ? v cc cb6 0.1 ? cb11 0.1 ? v cc r1 0 w (optional) cb10 0.1 ? v cc cb9 0.1 ? v cc v cc c2* 10 ? + cb8 0.1 ? cb7 0.1 ? l2 1 ? r2 0 w (optional) eqamp 100 w l1 1 ? c3* 10 ? c4* 10 ?
21 figure 13. HDMP-2630B/2631b package layout and marking, top view. rxcap0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 gnd_txhs HDMP-2630B/2631b xxxx-x rz.zz s yyww 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vrefr gnd_sstl rx[0] rx[1] rx[2] v cc _sstl rx[3] rx[4] rx[5] rx[6] v cc _sstl rx[7] rx[8] rx[9] gnd_sstl tbc tx[0] tx[1] tx[2] vreft tx[3] tx[4] tx[5] tx[6] rbc_sync tx[7] tx[8] tx[9] tx_rate gnd_txa txcap1 v cc _txhs so+ so v cc _txhs v cc gnd v cc eqamp rx_rate si+ *v cc si gnd_rxa v cc _rxa rxcap1 txcap0 v cc _txa ewrap v cc gnd refclk[1] refclk[0] en_cdet gnd com_det v cc ref_rate rbc[1] rbc[0] gnd_sstl xxxx-x = wafer lot number?uild number rz.zz = die revision s = supplier code yyww = date code (yy = year, ww = work week) country = country of manufacture (marked on back of device) rx_los
e1 e pin #1 d1 d b c l a2 a1 e 0.25 guage plane 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 a a a1 a2 d/e d1/e1 l b c e value 2.35 0.25 2.00 17.20 13.80 0.88 0.37 0.20 0.80 tolerance max. max. ?0.10 ?0.25 ?0.05 ?0.15 max. + 0.08/ ?0.03 basic dimensional parameter (millimeters) seating plane mechanical dimensions of HDMP-2630B/2631b package information item details package material metric metal qfp lead finish material 85% tin, 15% lead lead finish thickness 200-800 micro-inches lead skew 0.20 mm max. lead coplanarity 0.08 mm max. (seating plane method) 22
www.agilent.com/semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (408) 654-8675 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 271 2451 india, australia, new zealand: (+65) 271 2394 japan: (+81 3) 3335-8152(domestic/interna- tional), or 0120-61-1280(domestic only) korea: (+65) 271 2194 malaysia, singapore: (+65) 271 2054 taiwan: (+65) 271 2654 data subject to change. copyright ? 2002 agilent technologies, inc. january 17, 2002 5988-4935en

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